1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device using a porous semiconductor oxide film as an interlayer insulating film and a method of manufacturing the same.
2. Description of the Related Art
Recently, a design rule has been shortened to 0.25 xcexcm or less in a semiconductor device such as a micro processor. For this reason, severe problems occur in a process of manufacturing the semiconductor device having such a finer design rule. The problems cannot be solved by a conventional manufacturing technique. For example, one of the problems is a delay due to Rxc3x97C, where R is a wiring resistance and C is a wiring capacitance. This problem becomes an obstacle to an improvement in a LSI performance based on a high speed operation of transistors. Unless any counter-plan is carried out, the Moore""s law can not be maintained.
A technique to increase an operational frequency of an LSI is clear in the manufacturing process of an LSI having 0.25 xcexcm design rule. It is enough to miniaturize the transistor and then shorten the length of a gate. Thus, a switching speed of the transistor can be increased. However, recently, this method cannot be applied any longer. Increase of the switching speed of the transistor contributes only a little to the improvement of the operation speed of the LSI. This is because most of processors have critical paths through which signals are transmitted from an end of the LSI to another end thereof. Thus, the delay due to the time constant RC in a wiring pattern largely contributes to the operation speed of the LSI. Typically, reduction of a design rule makes the operational frequency higher. This is because the maximum length of a signal transmission path becomes shorter. However, when it is intended to produce a new LSI having a size larger than that of the conventional LSI by a new manufacturing process, it becomes difficult to improve the operational frequency of the new LSI.
The metal wiring patterns in such an LSI are roughly classified into a very fine wiring pattern group, a slightly thick wiring pattern group and a bus line. The very fine wiring pattern group is referred to as local wiring patterns through which a data within a function block is transmitted. The slightly thick wiring pattern group is referred to as global wiring patterns, through which a clock signal and power are supplied to the function block. The bus line is used to transmit data between the function blocks. These wiring patterns are generally formed on an insulating layers referred to as an interlayer insulating film.
Now, a width and thickness of the local wiring pattern used for the most advanced LSI having the design rule of 0.18 xcexcm is approximately 0.2 xcexcm. Such local wiring patterns are laid in the same interval of 0.2 xcexcm. On the other hand, the global wiring pattern has various widths from 5 to 100 xcexcm. Multi-layer metal wiring patterns are electrically connected through metals such as tungsten (W) embedded in fine holes referred to as a via hole or a through hole and formed in an interlayer insulating film.
These metal wiring patterns are further made finer for an LSI with the design rule of 0.1 xcexcm. A problem in making the multi-layer wiring pattern fine is the increase of the RC delay due to increase of the wiring resistance of a global wiring pattern. The wiring resistance increases with increase of the chip size of the LSI, and an inter-pattern capacitance increases due to the reduction of a gap between the local wiring patterns.
As a method of reducing the wiring pattern resistance R, it is enough to select a wiring pattern material having a smaller resistivity. For example, it is considered to use Cu or Au instead of Al that has been used up to now, and it is actually used in a partial field. Although Cu is a material having a very small resistance so that Cu is effective in reducing the wiring pattern resistance, it is easy to be diffused into Si. Thus, a barrier layer is needed on the surface of a silicon film. Although Au has a small resistance, it requires the barrier layer similarly to Cu. Therefore, Au does not have an advantage over Cu.
Reduction of the wiring pattern capacitance C is possible by replacing a SiO2 film with a low dielectric material such as a fluorine doped SiO2 or an organic insulating film. The fluorine doped SiO2 film has a dielectric constant lower than that of SiO2. However, the fluorine doped SiO2 film would be still high in a dielectric constant in future. Also, the organic insulating film lacks in the stableness at a high temperature and the wiring pattern material diffuses into the organic insulating film. Although the most excellent dielectric substance is vacuum, it is the atmosphere in view of the practical use. The relative dielectric constant thereof is substantially equal to xe2x80x9c1xe2x80x9d.
The technique referred to as an air bridge is known in which all the dielectric films are removed to float a wiring pattern in the space. However, it requires a number of poles such that a resonance frequency of the wiring pattern extremely exceeds a signal frequency used in the chip so as to support and protect the wiring pattern and protect against destruction resulting from a vibration. Although this method is already successful, it results in a high manufacturing cost. Therefore, it will be a long time before this method is actually used.
The reason of the increase of RC product due to the change of the design rule will be described below. Although an actual LSI has the five to six wiring pattern layers, the case of the two layers will be considered below in order to simplify the analysis.
The important dimension in the wiring pattern is a wiring pattern pitch, which determines the shortest distance between the wiring patterns and the minimum size of the chip. A usual wiring pattern pitch is approximately two times the width of the wiring pattern. The change from the manufacturing process for a 0.5-xcexcm wiring pattern to that for a 0.25-xcexcm wiring pattern reduces the wiring pattern width W to a half. Since an area of the chip is proportional to the square of W at this time, the area of the chip is reduced to the quarter.
On the other hand, the resistance of the metal wiring pattern is inversely proportional to a sectional area (TW). The increase of the resistance leads to the main cause of the delay. Unavoidably, the resistance must be reduced by maintaining the thickness T of a metal pattern or making it thicker. However, the increase of the film thickness of the wiring pattern increases a capacitance between the wiring patterns in a horizontal direction. This is because an area of portions opposite to and parallel to each other is increased irrespective of the reduction of the width between the metal wiring patterns.
As mentioned above, the increase of the capacitance and the increase of the resistance are in the relation of trade-off. Therefore, the approach of suppression of the RC product from the wiring pattern design reaches its limit.
Now, the material used for an interlayer insulating film is SiO2, and the relative dielectric constant thereof is approximately 4.0. This value is still high. Thus, it is said that SiO2 could be used until the present generation of 0.25 xcexcm at the most. Therefore, various materials other than fluorine doped SiO2 are studied to reduce the dielectric constant.
SiOF has a merit that the conventional process can be substantially directly used, and is put to a practical use in a partial field. It can be manufactured by using a PE-CVD (Plasma Enhanced Chemical Vapor Deposition) method, similarly to SiO2. As a material gas, C2F6 is used in addition to the SiO2 material gas such as TEOS (Tetraethoxysilane; Si(OC2H5)4). It is reported that a vast addition of the fluorine reduces an E value to about 2.7. However, the moisture absorption is increased in conjunction with the increase of F element amount. This results in the increase of the dielectric constant. The practical value is in a range 3.2 to 3.4, resulting in the insufficient effect of the E reduction. Moreover, it is necessary to protect the wiring pattern against corrosion due to free fluorine.
The smaller dielectric constant of an interlayer insulating film using SOG (Spin on Glass) is rapidly vigorously studied in recent years. The most commonly studied material is an inorganic system hydrogen containing SOG (Hydrogen Silsesquioxane; HSQ). Its chemical formula is (HSiO1.5)2n (n equal to 3 to 8). After a coating process, a strong shrinkage stress is brought about when a heat treatment is performed. If the hydrogen containing SOG film is filled between the wiring patterns, the shrinkage stress can not be released. Accordingly, it becomes porous. Thus, the dielectric constant in the horizontal direction is considered to be especially reduced. Therefore, the dielectric constant is 2.2 in the horizontal direction and 2.7 in the vertical direction. Since there is also an example suitable for a mass production, the anxiety of reliability is considered to be little. However, {circle around (1)} the shrinkage stress causes a crack to be brought about, {circle around (2)} the heat-proof temperature is lower than 400xc2x0 C., and {circle around (3)} the heat treatment must be performed in ambience with no oxygen because of the hydrogen containing. Therefore, the process must be strictly managed because of the above mentioned reasons.
In the above-mentioned air bridge method, a dielectric material portion is removed so as to float a wiring pattern in the space. The atmosphere basically exists between the wiring patterns. The relative dielectric constant is substantially xe2x80x9c1xe2x80x9d. Now, it is barely used in a high speed bipolar type circuit.
Actually, the long distance air bridge must be supported by posts. The weight of the wiring patterns can be supported without the poles. However, if the distance between the wiring patterns is short, the influence of electromagnet force becomes strong so that a wiring pattern having no pole may be bent. Moreover, there is a problem of a resonance frequency. If electric signals transmitted on the wiring patterns adjacent to each other are oscillated at the resonance frequency, the wiring pattern is broken. For this reason, it is necessary that the poles are provided at an adequate interval so that the resonance frequency is extremely higher than the signal frequency of the chip. Thus, although the capacitance is slightly increased by the posts, the entire dielectric constant is merely larger by 10 to 20% than the atmosphere.
On the other hand, a problem in the air bridge method is in complication of the process. It is necessary to remove by etching, the dielectric layer while leaving the portion of the posts. Another problem is that the air bridge must-be sealed. This may be not used for a long time because of the increase in cost. However, this is the most attractive in decreasing the dielectric constant.
As mentioned above, a new material for the interlayer insulating film is required to have the properties listed below:
a small dielectric constant;
an adaptation to a wiring pattern material;
a heat-proof property; and
an adaptation to a process.
The large reduction of the dielectric constant cannot be expected in the method of doping fluorine elements on a silicon oxide film. Therefore, it is expected to reduce the dielectric constant by decreasing a density. Also, the small dielectric constant is expected in the organic material. As for the adaptation to the wiring pattern material, metal ions are easy to be doped by electro-migration in a case of the organic material so that the insulating film is damaged. As for the heat-proof property, the glass transition temperature of the interlayer insulating film must be equal to or higher than 400xc2x0 C. in relation to the process. Softening of the interlayer insulating film and increase of a thermal expansion coefficient of insulating film material are brought about by heating the insulating film. The temperature at this time is the glass transition temperature. If a process temperature exceeds the glass transition temperature, the wiring pattern is largely deformed and destroyed. Thus, the stability at the high temperature is required to the interlayer insulating film. In this point, the silicon oxide film is superior to other material films. As for the adaptation to the process, the practical use is difficult unless the cost performance is excellent, in view of the adaptation to other manufacturing processes.
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide a semiconductor device including an interlayer insulating film with a small dielectric constant.
Another object of the present invention is to provide a semiconductor device including an interlayer insulating film with a heat-proof property.
Still another object of the present invention is to provide a semiconductor device including an interlayer insulating with an adaptability to a currently used process.
It is also an object of the present invention to provide a method of manufacturing the above semiconductor devices.
In order to achieve an aspect of the present invention, a method of manufacturing a semiconductor device, includes the steps of:
forming semiconductor circuit elements or wiring patterns on a semiconductor substrate;
forming a porous semiconductor oxide film as an interlayer insulating film on the semiconductor substrate including the semiconductor circuit elements or wiring patterns by oxidizing semiconductor substance in a mixture gas containing an oxygen gas in a chamber.
The porous semiconductor oxide film is a porous silicon oxide film.
The step of forming a porous semiconductor oxide film includes:
supplying the mixture gas containing the oxygen gas into the chamber; and
vaporizing silicon as the semiconductor substance in the chamber.
In this case, the pressure of the mixture gas in the chamber is preferably in a range 0.3 Torr to 10 Torr, and more preferably in a range 0.5 Torr to 10 Torr.
The pressure of the mixture gas in the chamber may be set to a predetermined value, or be changed while the mixture gas is supplied. At this time, the pressure of the mixture gas may be set to a first predetermined value and then to a second predetermined value larger than the first predetermined value. Further, the pressure of the mixture gas may be set to a third predetermined value small than the second predetermined value after being set to the second predetermined value.
Also, the mixture gas containing the oxygen gas into the chamber may be supplied such that the porous silicon oxide film covers the semiconductor circuit elements or wiring patterns while filling between the semiconductor circuit elements or wiring patterns. Instead, the mixture gas containing the oxygen gas into the chamber may be supplied such that the porous silicon oxide film covers the semiconductor circuit elements or wiring patterns while forming air portions on side walls of the semiconductor circuit elements or wiring patterns.
The aspect ratio of a space between the semiconductor circuit elements or wiring patterns is preferably equal to or smaller than 1.6, more preferably equal to or smaller than 0.8.
It is desirable that the mixture gas includes an inert gas and the oxygen gas, and contains the oxygen gas substantially equal to 1%.
Also, it is desirable that the porous semiconductor oxide film includes holes of an average diameter equal to or less than 20 nm, and includes SiO2 equal to or more than 85%. In addition, the porous silicon oxide film is formed to have a relative dielectric constant equal to or smaller than 1.95.
In order to achieve another aspect of the present invention, a method of manufacturing a semiconductor device, includes the steps of:
forming semiconductor circuit elements or wiring patterns on a semiconductor substrate;
supplying a mixture gas containing an oxygen gas into a chamber;
vaporizing silicon in the chamber to produce silicon oxide particles; and
forming a porous silicon oxide film as an interlayer insulating film on the semiconductor substrate including the semiconductor circuit elements or wiring patterns from the silicon oxide particles in a chamber.
In order to achieve still another aspect of the present invention, a semiconductor device includes semiconductor circuit elements or wiring patterns formed on a semiconductor substrate, and a porous silicon oxide film formed as an interlayer insulating film on the semiconductor substrate including the semiconductor circuit elements or wiring patterns. The porous silicon oxide film includes holes of an average diameter equal to or less than 20 nm.
The porous silicon oxide film may cover the semiconductor circuit elements or wiring patterns while filling between the semiconductor circuit elements or wiring patterns. Instead, the porous silicon oxide film may cover the semiconductor circuit elements or wiring patterns while forming gaps on side walls of the semiconductor circuit elements or wiring patterns.
In this case, an aspect ratio of a space between said semiconductor circuit elements or wiring patterns is equal to or smaller than 1.6, and the porous silicon oxide film includes SiO2 equal to or more than 85% to have a relative dielectric constant equal to or smaller than 1.95.